Pillar and Foudation of Truth
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Which prot/evan denomination [or non denomination] is the pillar and foundation of truth? 1 tim. 3 15 Assemblies of God Lutheran Southern Baptist Independent Baptist Vineyard Calvary Chapel Ill let some one else add a few more if they want.
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wygantsh
quote:
Originally posted by wygantsh
It takes a lot more than cutting and pasting other peoples writings to have a real personal experience and understanding of what truly motivates people to redact history and/or scriptures.
By a lot more do you mean asserting things from anti-Catholic and Gnostic sources inaccurately from memory?
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The sycophantic apologetics who obfuscate, deny, minimize and blame the otrocities of the Church sponsored murders of the innocent and the Church sponsored homosexuality currently being taught in the diocesan seminaries . . .
'Church sponsored'? Oh c'mon. Show me one official document that promotes murder and homosexuality - in the priesthood or anywhere else. We, like in times past, have a problem with abuse or laxity of following our own teachings, but don't construe this into the Church 'sponsoring' it.
That is where you and others keep missing the point. Infallibility does not cover those members of the Church who do not follow the Church's teachings.
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and practiced by 35% of the Catholic priesthood, are not Christian and they are certainly not Catholic.
Wow, did I just hear you say that??????
You've got some nerve.
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A good example of this is a local priest here who was abusing children at the Church and the police came and arrested him and the church covered it up and never notified the parish that the priest was incarcerated and convicted of felony CSC.
Those within your local diocese and your (most likely) former bishop may have covered it up, but it is wrong for you to say 'the Church' covered it up. Lacking all the details, it sounds as if those in the hierarchy betrayed your confidence, for which they should be disciplined.....again, abuses.
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The encyclical of JOHN XXIII on holy orders specifically states that a neophyte cannot enter the priesthood if he has any thoughts of homosexuality or any other prurient perverted behavior. PERIOD.
I've posted that document several times - but it's not an encyclical, but a guideline for the ordination of the priesthood. As a guideline, I don't know how binding it was, however. At any rate, it was ignored and all kinds of grief came upon the Church as a result. But disciplines can change and the language we use to address issues can change. The Holy See released a document a year or so ago that was phrased more moderately than that document.
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The criminal code in this state still lists sodomy as a felony; which in the statutory language is called; 'crime against nature'.
This is virtually irrelevant. There are laws now on the books that approve of gay unions and it looks like they will allow gay marriages in the future. We can't appeal to secular laws as they shift all the time.
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quote:
QUOTE FROM ALCOVEY: 'Church sponsored'? Oh c'mon. Show me one official document that promotes murder and homosexuality - in the priesthood or anywhere else. We, like in times past, have a problem with abuse or laxity of following our own teachings, but don't construe this into the Church 'sponsoring' it.
WYGANTSH RESPONSE: 'Sponsorship' of murder and homosexuality means advocating, promoting, condoning and/or being complicit in the commission of these crimes. For example the Bishop in our dioscese is a practicing homosexual and three of the priests who serve under him are practicing homosexuals, and 2 of the diocesan canon lawyers who sit on the tribunal for the diocese are practicing homosexuals. They are a group who accept, practice and believe in homosexual behavior and lifestyle within their profession as a clergy of the Catholic church. PERIOD. You can't spin that. This is evil and wrong and yet the people feel helpless to change it because even if we bring a cause of action to the tribunal, two of the 3 canon law priests hearing the petition are homosexuals. This is sponorship and promoting of homosexuality because it attracts young homosexual men into the priesthood because they know they will have a job for life, a nice house, a nice car, homosexual friends in their profession who support them, etc... WAKE UP! OPEN YOUR EYES!
I have served four different parishes in four different dioceses in this state for the past 33 years and I am speaking from what I have seen and witnessed not something I read in a book or the internet. The Catholic Church are bishops and priests who serve under the Canon law which says they ARE the OFFICE OF CHRIST. You cannot make a legitimate claim that they don't represent the church because they do. This argument of yours is lunacy. The Church Universal is incorruptible because it is the spiritual church and resides in Spirit. The Church Militant is CORRUPTIBLE because it resides in the Flesh and as Jesus said; "Spirit is spirit and flesh is flesh". You use the term CHURCH to try and say that the Church Militant and the Church Universal are one Church, they are not and that is where the confusion is and why sheep run off the cliffs when the wolves say jump, you won't die.
Pope Leo specifically addressed this in his apostolic writings and encyclicals in 1890:POPE LEO EXCERPT: "Behold, this primeval enemy and slayer of man has taken courage, Transformed into an angel of light, he wanders about with all the multitude of wicked spirits, invading the earth in order to blot out the name of God and of his Christ, to seize upon, slay and cast into eternal perdition souls destined for the crown of eternal glory. This wicked dragon pours out, as a most impure flood, the venom of his malice on men of depraved mind and corrupt heart, the spirit of lying, of impiety, of blasphemy, and the pestilent breath of impurity, and of every vice and iniquity. These most crafty enemies have filled and inebriated with gall and bitterness the Church, the spouse of the Immaculate Lamb, and have laid impious hands on her most sacred possessions. In the Holy Place itself, where has been set up the See of the most holy Peter and the Chair of Truth for the light of the world, they have raised the throne of their abominable impiety, with the iniquitous design that when the Pastor has been struck, the sheep may be scattered. Arise then, O invincible prince (archangel Michael), bring help against the attacks of the lost spirits to the people of God, and bring them the victory."
Why do you suppose they took out of the canon this prayer to Archangel Michael? Why do you suppose that these bishops and priests hate the Blessed Mother? They hate her because they hate God and
Edited by wygantsh on 03/20/2007 08:59:32
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quote:
Originally posted by wygantsh
WYGANTSH RESPONSE: 'Sponsorship' of murder and homosexuality means advocating, promoting, condoning and/or being complicit in the commission of these crimes. For example the Bishop in our dioscese is a practicing homosexual and three of the priests who serve under him are practicing homosexuals, and 2 of the diocesan canon lawyers who sit on the tribunal for the diocese are practicing homosexuals. They are a group who accept, practice and believe in homosexual behavior and lifestyle within their profession as a clergy of the Catholic church. PERIOD. You can't spin that.
I don't need to spin that, I deplore it.
Congratulations, you just found another abuse.
There have been corrupt bishops throughout the history of the Church. While this is deplorable and regrettable, this is not 'the Church' who is promoting these things. The Church of Christ is holy, and cannot promote error.
The definition of the Church is that it is the lay faithful and the bishops and priests who are in communion with the vicar of Christ and holy Mother Church. When some bishop is an active homosexual, he is not in communion with the Church. In fact, not everything a Pope does is either. We must make a distinction between errant members of the Church and the Church - even though it is also a visible community.
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. . . This is sponorship and promoting of homosexuality because it attracts young homosexual men into the priesthood because they know they will have a job for life, a nice house, a nice car, homosexual friends in their profession who support them, etc... WAKE UP! OPEN YOUR EYES!
I have served four different parishes in four different dioceses in this state for the past 33 years and I am speaking from what I have seen and witnessed not something I read in a book or the internet.
If you knew how forcefully I have spoken out on these issues, you would realize that you are preaching to the choir.
My issue is that you are not framing the problem in a theologically correct manner. You are indicting the whole Church (that Christ founded) with the sins of the few. We don't forsake and indict Peter because of Judas. Judas will get his reward, but we need to look to Christ and pray for Peter so that his faith will not fail him and he can strengthen his brethren, if you get my drift.
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The Catholic Church are bishops and priests who serve under the Canon law which says they ARE the OFFICE OF CHRIST. You cannot make a legitimate claim that they don't represent the church because they do.
Judas was sent out with the others. Did he, or did he not represent Christ?
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This argument of yours is lunacy. The Church Universal is incorruptible because it is the spiritual church and resides in Spirit. The Church Militant is CORRUPTIBLE because it resides in the Flesh and as Jesus said; "Spirit is spirit and flesh is flesh". You use the term CHURCH to try and say that the Church Militant and the Church Universal are one Church, they are not and that is where the confusion is. . .
No, the confusion is on your part. I actually appreciate what you trying to say, but the Church has done a better job of explaining it t
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quote:
ALCOVEY QUOTE: OK, I need to call bullsh*t. I've been as hard as anybody on the abuses and corruption in the hierarchy, but to say categorically that these bishops and priests 'hate the Blessed Mother and hate God' is over the top and 'voodoo priests' is just plain funny. Nothing will discredit your message quicker than overstating and exaggerating your case
WYGANTSH RESPONSE: There is nothing funny about voodoo priests. If you knew what they were and what they did and how they practice their arts you would begin to identify the foul spirits that fill the Catholic Clergy and their kinship to each other.
The voodoo priests and the homosexual catholic priests and rock stars such as Madonna have a common hatred of God and their jealousy and inner rage is to corrupt the children of God, to x out the Holy Spirit from the temples of God's children and make us feel sorry for them - SYMPATHY FOR THE DEVIL -.
There is NO difference in the fornication and adultery that accompanies the voodoo rituals and the fornication and adultery that accompanies the catholic priests ministry they are both filled with the spirits of sodoma, ghommora, masturba, sapphos, lesbos, and voodoo. The Catholic Church is doing NOTHING to exorcise the problem because the first step is to RECOGNIZE and start excommunicating the malevolent priests who hate God.
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LMC6035 pinout
LMC6035 pdf
LMC6035 circuit
LMC6035/LMC6036
Low Power 2.7V Single Supply CMOS Operational
Amplifiers
October 2002
General Description
The LMC6035/6 is an economical, low voltage op amp ca- pable of rail-to-rail output swing into loads of 600?? LMC6035 is available in a chip sized package (8-Bump micro SMD) using National?? micro SMD package technol- ogy. Both allow for single supply operation and are guaran- teed for 2.7V, 3V, 5V and 15V supply voltage. The 2.7 supply voltage corresponds to the End-of-Life voltage (0.9V/cell) for three NiCd or NiMH batteries in series, making the LMC6035/6 well suited for portable and rechargeable sys- tems. It also features a well behaved decrease in its speci- fications at supply voltages below its guaranteed 2.7V op- eration. This provides a ??omfort zone?? for adequate operation at voltages significantly below 2.7V. Its ultra low input currents (IIN) makes it well suited for low power active filter application, because it allows the use of higher resistor values and lower capacitor values. In addition, the drive capability of the LMC6035/6 gives these op amps a broad range of applications for low voltage systems.
Features
(Typical Unless Otherwise Noted)
n LMC6035 in micro SMD Package
n Guaranteed 2.7V, 3V, 5V and 15V Performance
n Specified for 2 k??and 600??Loads
n Wide Operating Range: 2.0V to 15.5V
n Ultra Low Input Current: 20fA
n Rail-to-Rail Output Swing
@ 600?? 200mV from either rail at 2.7V
@ 100k?? 5mV from either rail at 2.7V
n High Voltage Gain: 126dB
n Wide Input Common-Mode Voltage Range
-0.1V to 2.3V at VS = 2.7V
n Low Distortion: 0.01% at 10kHz
n LMC6035 Dual LMC6036 Quad
n See AN-1112 for micro SMD considerations
Applications
n Filters
n High Impedance Buffer or Preamplifier
n Battery Powered Electronics
n Medical Instrumentation
Connection Diagram
8-Bump microSMD
microSMD Connection Table
Bump Number LM6035IBP LMC6035IBPX
LMC6035ITL LMC6035ITLX
Top View
01283065
A1 OUTPUT A OUTPUT B B1 IN A?? V+
C1 IN A+ OUTPUT A
C2 V?? IN A??C3 IN B+ IN A+ B3 IN B?? V??A3 OUTPUT B IN B+
A2 V+ IN B?? (Bump Side Down)
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.
ESD Tolerance (Note 2)
Human Body Model 3000V Machine Model 300V Differential Input Voltage ? Supply Voltage Supply Voltage (V+ ??V?? 16V Output Short Circuit to V + (Note 8) Output Short Circuit to V ?? (Note 3)
Lead Temperature (soldering, 10
sec.) 260?C
Junction Temperature (Note 4) 150?C
Operating Ratings (Note 1)
Supply Voltage 2.0V to 15.5V Temperature Range
LMC6035I and LMC6036I ??0?C ??T J ??+85?C Thermal Resistance (?JA)
8-pin MSOP 230?C/W
8-pin SOIC 175?C/W
14-pin SOIC 127?C/W
14-pin TSSOP 137?C/W
8-Bump (6 mil) micro SMD 220?C/W
Current at Output Pin ?18mA Current at Input Pin ?5mA Current at Power Supply Pin 35mA Storage Temperature Range ??5?C to +150?C
8-Bump (12 mil) Thin micro
220?C/W
DC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ = 25?C, V+ = 2.7V, V??= 0V, VCM = 1.0V, VO = 1.35V and RL > 1M??
Boldface limits apply at the temperature extremes.
LMC6035I/LMC6036I
Symbol Parameter Conditions
(Note 6)
(Note 5)
(Note 6)
VOS Input Offset Voltage 0.5 5 mV
TCVOS Input Offset Voltage
Average Drift
2.3 ?V/?C
IIN Input Current (Note 11) 0.02 90 pA IOS Input Offset Current (Note 11) 0.01 45 PA RIN Input Resistance > 10 Tera ?? CMRR Common Mode Rejection
+PSRR Positive Power Supply
Rejection Ratio
??SRR Negative Power Supply
Rejection Ratio
VCM Input Common-Mode
Voltage Range
0.7V ??VCM ??12.7V, V+ = 15V
5V ??V+ ??15V, VO = 2.5V
0V ??V??????0V,
VO = 2.5V, V+ = 5V V+ = 2.7V
For CMRR ??40dB
63 96 dB
63 93 dB
74 97 dB
??.1 0.3
V+ = 3V
For CMRR ??40dB
??.3 0.1
V+ = 5V
For CMRR ??50dB
??.5 ??.2
V+ = 15V
For CMRR ??50dB
??.5 ??.2
DC Electrical Characteristics (Continued)
Unless otherwise specified, all limits guaranteed for TJ = 25?C, V+ = 2.7V, V??= 0V, VCM = 1.0V, VO = 1.35V and RL > 1M??
Boldface limits apply at the temperature extremes.
LMC6035I/LMC6036I
Symbol Parameter Conditions
(Note 6)
(Note 5)
(Note 6)
AV Large Signal Voltage Gain
(Note 7)
RL = 600?? Sourcing 100
Sinking 25
1000 V/mV
250 V/mV
RL = 2k?? Sourcing 2000 V/mV Sinking 500 V/mV
V O Output Swing V + = 2.7V
RL = 600??to 1.35V
0.2 0.5
V + = 2.7V
RL = 2k??to 1.35V
0.07 0.2
V + = 15V
RL = 600??to 7.5V
0.36 1.25
V + = 15V,
RL = 2 k??to 7.5V
0.12 0.4
I O Output Current V O = 0V Sourcing 4
V O = 2.7V Sinking 3
IS Supply Current LMC6035 for Both Amplifiers
V O = 1.35V
LMC6036 for All Four Amplifiers
V O = 1.35V
0.65 1.6
1.3 2.7
AC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ = 25?C, V+ = 2.7V, V?? = 0V, VCM = 1.0V, V O = 1.35V and RL > 1 M??
Boldface limits apply at the temperature extremes.
Symbol Parameter Conditions Typ Units
(Note 5)
SR Slew Rate (Note 9) 1.5 V/?s GBW Gain Bandwidth Product V + = 15V 1.4 MHz ? m Phase Margin 48 ?
G m Gain Margin 17 dB
Amp-to-Amp Isolation (Note 10) 130 dB
e n Input-Referred Voltage Noise f = 1kHz 27
V CM = 1V
i n Input Referred Current Noise f = 1kHz 0.2
THD Total Harmonic Distortion f = 10kHz, AV = ??0
R L = 2k?? VO = 8 VPP 0.01 %
AC Electrical Characteristics (Continued)
Unless otherwise specified, all limits guaranteed for TJ = 25?C, V+ = 2.7V, V?? = 0V, VCM = 1.0V, V O = 1.35V and RL > 1 M??
Boldface limits apply at the temperature extremes.
Symbol Parameter Conditions Typ Units
(Note 5)
V + = 10V
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics.
Note 2: Human body model, 1.5k??in series with 100pF.
Note 3: Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150?C. Output currents in excess of 30mA over long term may adversely affect reliability.
Note 4: The maximum power dissipation is a function of TJ(MAX), ?JA, and TA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) ??A)/? JA. All numbers apply for packages soldered directly onto a PC board with no air flow.
Note 5: Typical Values represent the most likely parametric norm or one sigma value.
Note 6: All limits are guaranteed by testing or statistical analysis.
Note 7: V+ = 15V, VCM = 7.5V and R L connected to 7.5V. For Sourcing tests, 7.5V ??VO ??11.5V. For Sinking tests, 3.5V ??VO ??7.5V.
Note 8: Do not short circuit output to V+ when V+ is greater than 13V or reliability will be adversely affected.
Note 9: V+ = 15V. Connected as voltage follower with 10V step input. Number specified is the slower of the positive and negative slew rates.
Note 10: Input referred, V + = 15V and RL = 100k??connected to 7.5V. Each amp excited in turn with 1kHz to produce VO = 12 VPP.
Note 11: Guaranteed by design.
Typical Performance Characteristics Unless otherwise specified, VS = 2.7V, single supply, TA =
Supply Current vs. Supply Voltage (Per Amplifier) Input Current vs. Temperature
01283052 01283053
Sourcing Current vs. Output Voltage Sourcing Current vs. Output Voltage
01283054 01283055
Sinking Current vs. Output Voltage Sinking Current vs. Output Voltage
01283056 01283057
Typical Performance Characteristics Unless otherwise specified, VS = 2.7V, single supply, TA =
25?C (Continued)
Output Voltage Swing vs. Supply Voltage Input Noise vs. Frequency
01283058 01283059
Input Noise vs. Frequency Amp to Amp Isolation vs. Frequency
01283060 01283061
Amp to Amp Isolation vs. Frequency +PSRR vs. Frequency
01283062
01283032
Typical Performance Characteristics Unless otherwise specified, VS = 2.7V, single supply, TA =
25?C (Continued)
??SRR vs. Frequency CMRR vs. Frequency
01283033 01283034
CMRR vs. Input Voltage CMRR vs. Input Voltage
01283035 01283036
Input Voltage vs. Output Voltage Input Voltage vs. Output Voltage
01283014 01283015
Typical Performance Characteristics Unless otherwise specified, VS = 2.7V, single supply, TA =
25?C (Continued)
Frequency Response vs. Temperature Frequency Response vs. Temperature
01283016 01283017
Gain and Phase vs. Capacitive Load Gain and Phase vs. Capacitive Load
01283018 01283019
Slew Rate vs. Supply Voltage Non-Inverting Large Signal Response
01283020
01283037
Typical Performance Characteristics Unless otherwise specified, VS = 2.7V, single supply, TA =
25?C (Continued)
Non-Inverting Large Signal Response Non-Inverting Large Signal Response
01283021 01283022
Non-Inverting Small Signal Response Non-Inverting Small Signal Response
01283023 01283024
Non-Inverting Large Signal Response Inverting Large Signal Response
01283025 01283026
Typical Performance Characteristics Unless otherwise specified, VS = 2.7V, single supply, TA =
25?C (Continued)
Inverting Large Signal Response Inverting Large Signal Response
01283027 01283028
Inverting Small Signal Response Inverting Small Signal Response
01283029 01283030
Inverting Small Signal Response Stability vs. Capacitive Load
01283031
01283038
Typical Performance Characteristics Unless otherwise specified, VS = 2.7V, single supply, TA =
25?C (Continued)
Stability vs. Capacitive Load Stability vs. Capacitive Load
01283039 01283040
Stability vs. Capacitive Load Stability vs. Capacitive Load
Stability vs. Capacitive Load
01283041 01283042
01283043
1.0 Application Notes
1.1 Background
The LMC6035/6 is exceptionally well suited for low voltage applications. A desirable feature that the LMC6035/6 brings to low voltage applications is its output drive capability ??a hallmark for National?? CMOS amplifiers. The circuit of Fig- ure 1 illustrates the drive capability of the LMC6035/6 at 3V of supply. It is a differential output driver for a one-to-one audio transformer, like those used for isolating ground from the telephone lines. The transformer (T1) loads the op amps with about 600??of AC load, at 1 kHz. Capacitor C1 functions to block DC from the low winding resistance of T1. Although the value of C1 is relatively high, its load reactance (Xc) is negligible compared to inductive reactance (XI) of T1.
01283044
FIGURE 1. Differential Driver
The circuit in Figure 1 consists of one input signal and two output signals. U1A amplifies the input with an inverting gain of ??, while the U1B amplifies the input with a non-inverting gain of +2. Since the two outputs are 180? out of phase with each other, the gain across the differential output is 4. As the differential output swings between the supply rails, one of the op amps sources the current to the load, while the other op amp sinks the current.
How good a CMOS op amp can sink or source a current is an important factor in determining its output swing capability. The output stage of the LMC6035/6 ??like many op amps ??sources and sinks output current through two complementary transistors in series. This ??otem pole?? ar- rangement translates to a channel resistance (Rdson) at each supply rail which acts to limit the output swing. Most CMOS op amps are able to swing the outputs very close to the rails ??except, however, under the difficult conditions of low supply voltage and heavy load. The LMC6035/6 exhibits exceptional output swing capability under these conditions.
The scope photos of Figure 2 and Figure 3 represent mea- surements taken directly at the output (relative to GND) of U1A, in Figure 1. Figure 2 illustrates the output swing capa- bility of the LMC6035, while Figure 3 provides a benchmark comparison. (The benchmark op amp is another low voltage (3V) op amp manufactured by one of our reputable competi- tors.)
01283045
FIGURE 2. Output Swing Performance of the LMC6035 per the Circuit of Figure 1
01283046
FIGURE 3. Output Swing Performance of Benchmark
Op Amp per the Circuit of Figure 1
Notice the superior drive capability of LMC6035 when com- pared with the benchmark measurement ??even though the benchmark op amp uses twice the supply current.
Not only does the LMC6035/6 provide excellent output swing capability at low supply voltages, it also maintains high open loop gain (A VOL) with heavy loads. To illustrate this, the LMC6035 and the benchmark op amp were compared for their distortion performance in the circuit of Figure 1. The graph of Figure 4 shows this comparison. The y-axis repre- sents percent Total Harmonic Distortion (THD plus noise) across the loaded secondary of T1. The x-axis represents the input amplitude of a 1 kHz sine wave. (Note that T1 loses about 20% of the voltage to the voltage divider of RL (600?? and T1?? winding resistances ??a performance deficiency of the transformer.)
1.0 Application Notes (Continued)
01283047
FIGURE 4. THD+Noise Performance of LMC6035 and
??enchmark?? per Circuit of Figure 1
01283048
FIGURE 5. 2-Pole, 3kHz, Active, Sallen and Key, Lowpass Filter with Butterworth Response
1.2.1.1 Low-Pass Frequency Scaling Procedure
The actual component values represented in bold of Figure 5
were obtained with the following scaling procedure:
1. First determine the frequency scaling factor (FSF) for the desired cutoff frequency. Choosing fc at 3kHz, pro- vides the following FSF computation:
FSF = 2? x 3kHz (desired cutoff freq.) = 18.84 x 10 3
2. Then divide all of the normalized capacitor values by the
FSF as follows: C1?? = C(Normalized)/FSF C1?? =
Figure 4 shows the superior distortion performance of
0.707/18.84 x 103
= 37.93 x 10??
C2??= 1.414/18.84
LMC6035/6 over that of the benchmark op amp. The heavy
= 75.05 x 10
(C1??and C2?? prior to impedance
loading of the circuit causes the AVOL of the benchmark part to drop significantly which causes increased distortion.
1.2 APPLICATION CIRCUITS
1.2.1 Low-Pass Active Filter
A common application for low voltage systems would be active filters, in cordless and cellular phones for example. The ultra low input currents (IIN) of the LMC6035/6 makes it well suited for low power active filter applications, because it allows the use of higher resistor values and lower capacitor values. This reduces power consumption and space.
Figure 5 shows a low pass, active filter with a Butterworth (maximally flat) frequency response. Its topology is a Sallen and Key filter with unity gain. Note the normalized compo- nent values in parenthesis which are obtainable from stan- dard filter design handbooks. These values provide a 1Hz cutoff frequency, but they can be easily scaled for a desired cutoff frequency (fc). The bold component values of Figure 5 provide a cutoff frequency of 3kHz. An example of the scal- ing procedure follows Figure 5.
scaling)
3. Last, choose an impedance scaling factor (Z). This Z factor can be calculated from a standard value for C2. Then Z can be used to determine the remaining compo- nent values as follows:
Z = C2??C2(chosen) = 75.05 x 10 ??/6.8nF = 8.4k
C1 = C1??Z = 37.93 x 10?? /8.4k = 4.52nF
(Standard capacitor value chosen for C1 is 4.7nF ) R1 = R1(normalized) x Z = 1??x 8.4k = 8.4k?? R2 = R2(normalized) x Z = 1??x 8.4k = 8.4k??(Standard value chosen for R1 and R2 is 8.45k??)
1.2.2 High Pass Active Filter
The previous low-pass filter circuit of Figure 5 converts to a high-pass active filter per Figure 6.
01283049
FIGURE 6. 2 Pole, 300Hz, Sallen and Key, High-Pass Filter
1.0 Application Notes (Continued)
1.2.2.1 High-Pass Frequency Scaling Procedure
Choose a standard capacitor value and scale the imped- ances in the circuit according to the desired cutoff frequency (300Hz) as follows: C = C1 = C2 Z = 1 Farad/C(chosen) x 2? x (desired cutoff freq.) = 1 Farad/6.8nF x 2? x 300
Hz = 78.05k
R1 = Z x R1(normalized) = 78.05k x (1/0.707) = 110.4k??(Standard value chosen for R1 is 110k??)
R2 = Z x R2(normalized) = 78.05k x (1/1.414) = 55.2k??(Standard value chosen for R1 is 54.9k??)
1.2.3 Dual Amplifier Bandpass Filter
The dual amplifier bandpass (DABP) filter features the ability to independently adjust fc and Q. In most other bandpass topologies, the fc and Q adjustments interact with each other. The DABP filter also offers both low sensitivity to component values and high Qs. The following application of Figure 7, provides a 1kHz center frequency and a Q of 100.
01283050
FIGURE 7. 2 Pole, 1kHz Active, Bandpass Filter
1.2.3.1 DABP Component Selection Procedure
Component selection for the DABP filter is performed as follows:
1. First choose a center frequency (fc). Figure 7 represents component values that were obtained from the following computation for a center frequency of 1kHz. R2 = R3
= 1/(2 ?f cC) Given: fc = 1kHz and C (chosen) = 6.8nF
R2 = R3 = 1/(2? x 3kHz x 6.8nF) = 23.4k??(Chosen standard value is 23.7k??)
2. Then compute R1 for a desired Q (fc/BW) as follows:
R1 = Q x R2. Choosing a Q of 100, R1 = 100 x
23.7k?? = 2.37M??
1.3 PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-IMPEDANCE WORK
It is generally recognized that any circuit which must operate with < 1000pA of leakage current requires special layout of the PC board. If one wishes to take advantage of the ultra-low bias current of the LMC6035/6, typically < 0.04pA, it is essential to have an excellent layout. Fortunately, the techniques for obtaining low leakages are quite simple. First, the user must not ignore the surface leakage of the PC board, even though it may at times appear acceptably low. Under conditions of high humidity, dust or contamination, the surface leakage will be appreciable.
To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LMC6035 or LMC6036 inputs and the terminals of capacitors, diodes, conductors, resistors, relay terminals, etc. connected to the op amp?? inputs. See Figure 8. To have a significant effect, guard rings should be placed on both the top and bottom of the PC board. This PC foil must then be connected to a voltage which is at the same voltage as the amplifier inputs, since no leakage current can flow between two points at the same potential. For example, a PC board trace-to-pad resistance of 1012?? which is normally considered a very large resis- tance, could leak 5pA if the trace were a 5V bus adjacent to the pad of an input. This would cause a 100 times degrada- tion from the amplifiers actual performance. However, if a guard ring is held within 5mV of the inputs, then even a resistance of 1011??would cause only 0.05pA of leakage current, or perhaps a minor (2:1) degradation of the amplifi- er?? performance. See Figure 9a, b, c for typical connections of guard rings for standard op amp configurations. If both inputs are active and at high impedance, the guard can be tied to ground and still provide some protection; see Figure 9 d.
01283007
FIGURE 8. Example, using the LMC6036 of Guard Ring in P.C. Board Layout
1.0 Application Notes (Continued)
(c) Follower
01283010
(a) Inverting Amplifier
01283008
(b) Non-Inverting Amplifier
01283009
(d) Howland Current Pump
01283011
FIGURE 9. Guard Ring Connections
1.3.1 CAPACITIVE LOAD TOLERANCE
Like many other op amps, the LMC6035/6 may oscillate when its applied load appears capacitive. The threshold of oscillation varies both with load and circuit gain. The con- figuration most sensitive to oscillation is a unity-gain follower. See the Typical Performance Characteristics.
The load capacitance interacts with the op amp?? output resistance to create an additional pole. If this pole frequency is sufficiently low, it will degrade the op amp?? phase margin so that the amplifier is no longer stable at low gains. As shown in Figure 10, the addition of a small resistor (50??€?00?? in series with the op amp?? output, and a ca- pacitor (5pF??0pF) from inverting input to output pins, re- turns the phase margin to a safe value without interfering with lower-frequency circuit operation. Thus, larger values of capacitance can be tolerated without oscillation. Note that in all cases, the output will ring heavily when the load capaci- tance is near the threshold for oscillation.
1.4 Micro SMD Considerations
Contrary to what might be guessed, the micro SMD package does not follow the trend of smaller packages having higher thermal resistance. LMC6035 in micro SMD has thermal resistance of 220?C/W compared to 230?C/W in MSOP. Even when driving a 600?? load and operating from ?7.5V sup-
plies, the maximum temperature rise will be under 4.5?C. For application information specific to micro SMD, see Applica- tion note AN-1112.
01283005
FIGURE 10. Rx, Cx Improve Capacitive Load Tolerance
Capacitive load driving capability is enhanced by using a pull up resistor to V+ (Figure 11). Typically a pull up resistor conducting 500?A or more will significantly improve capaci- tive load responses. The value of the pull up resistor must be determined based on the current sinking capability of the amplifier with respect to the desired output swing. Open loop gain of the amplifier can also be affected by the pull up resistor (see Electrical Characteristics).
1.0 Application Notes (Continued)
01283006
FIGURE 11. Compensating for Large Capacitive Loads with a Pull Up Resistor
Connection Diagrams
8-Pin SO/MSOP 14-Pin SO/TSSOP
Top View
01283001
Top View
01283002
Ordering Information
Package Temperature Range Transport Media NSC Drawing
Industrial
??0?C to +85?C
8-pin Small Outline (SO) LMC6035IM Rails
8-pin Mini Small Outline
LMC6035IMX 2.5k Units Tape and Reel
LMC6035IMM 1k Units Tape and Reel
LMC6035IMMX 3.5k Units Tape and Reel
14-pin Small Outline (SO) LMC6036IM Rails
LMC6036IMX 2.5k Units Tape and Reel
14-pin Thin Shrink Small
Outline (TSSOP)
8-Bump micro SMD (Small Bump)
8-Bump Thin micro SMD (Large Bump)
LMC6036IMT Rails LMC6036IMTX 2.5k Units Tape and Reel LMC6035IBP 250 Units Tape and Reel LMC6035IBPX 3k Units Tape and Reel LMC6035ITL 250 Units Tape and Reel LMC6035ITLX 3k Units Tape and Reel
BPA08FFB TLA08JQA
Physical Dimensions inches (millimeters)
unless otherwise noted
8-Lead (0.150" Wide) Molded Small Outline Package, JEDEC NS Package Number M08A
8-Lead (0.150" Wide) Molded Mini Small Outline Package, JEDEC NS Package Number MUA08A
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead (0.150" Wide) Molded Small Outline Package, JEDEC NS Package Number M14A
14-Pin TSSOP
NS Package Number MTC14
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
NOTE: UNLESS OTHERWISE SPECIFIED.
1. EPOXY COATING.
2. 63Sn/37Pb EUTECTIC BUMP.
3. RECOMMEND NON-SOLDER MASK DEFINED LANDING PAD.
4. PIN A1 IS ESTABLISHED BY LOWER LEFT CORNER WITH RESPECT TO TEXT ORIENTATION PINS ARE NUMBERED COUNTERCLOCKWISE.
5. XXX IN DRAWING NUMBER REPRESENTS PACKAGE SIZE VARIATION WHERE X1 IS PACKAGE WIDTH, X2 IS PACKAGE LENGTH AND X3 IS PACKAGE HEIGHT.
6. REFERENCE JEDEC REGISTRATION MO-211, VARIATION BC.
8-Bump micro SMD (6 mil bumps) NS Package Number BPA08FFB
X1 = 1.412mm X2 = 1.412mm X3 = 0.850mm
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
NOTE: UNLESS OTHERWISE SPECIFIED.
1. EPOXY COATING.
2. 63Sn/37Pb EUTECTIC BUMP.
3. RECOMMEND NON-SOLDER MASK DEFINED LANDING PAD.
4. PIN A1 IS ESTABLISHED BY LOWER LEFT CORNER WITH RESPECT TO TEXT ORIENTATION PINS ARE NUMBERED COUNTERCLOCKWISE.
5. XXX IN DRAWING NUMBER REPRESENTS PACKAGE SIZE VARIATION WHERE X1 IS PACKAGE WIDTH, X2 IS PACKAGE LENGTH AND X3 IS PACKAGE HEIGHT.
6. REFERENCE JEDEC REGISTRATION MO-211, VARIATION BC.
8-Bump Thin micro SMD (12 mil bumps) NS Package Number TLA08JQA
X1 = 1.717mm X2 = 1.869mm X3 = 0.600mm
LIFE SUPPORT POLICY
NATIONAL?? PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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NE334S01 circuit
PRELIMINARY DATA SHEET
C BAND SUPER LOW NOISE HJ FET
NE334S01
FEATURES
?? VERY LOW NOISE FIGURE:
0.25 dB TYP at 4 GHz
?? HIGH ASSOCIATED GAIN:
16.0 dB TYP at 4 GHz
MAXIMUM AVAILABLE GAIN, FORWARD INSERTION GAIN vs. FREQUENCY
VDS = 2 V ID = 10 mA
?? GATE WIDTH: 280 ??
?? TAPE & REEL PACKAGING OPTION AVAILABLE
?? LOW COST PLASTIC PACKAGE
|S21S|2
DESCRIPTION
1 2 4
6 8 10 14
20 30
The NE334S01 is a Hetero-Junction FET that uses the junction between Si-doped AlGaAs and undoped InGaAs to create very high mobility electrons. Its excellent low noise and high asso- ciated gain make it suitable for TVRO and other commercial systems.
NEC's stringent quality assurance and test procedures assure the highest reliability and performance.
Frequency, f (GHz)
RECOMMENDED
OPERATING CONDITION (TA = 25??)
SYMBOLS CHARACTERISTIC UNITS MIN TYP MAX
VDS Drain to Source Voltage V 2 2.5
ID Drain Current mA 15 20
PIN Input Power dBm 0
ELECTRICAL CHARACTERISTICS (TA = 25??)
PART NUMBER NE334S01
PACKAGE OUTLINE S01
SYMBOLS PARAMETERS AND CONDITIONS UNITS MIN TYP MAX
NF1 Noise Figure, VDS = 2.0 V, ID = 15 mA, f = 4 GHz dB 0.25 0.35
GA1 Associated Gain, VDS = 2.0 V, ID = 15 mA, f = 4 GHz dB 15.0 16.0
IDSS Saturated Drain Current, VDS = 2.0 V, VGS = 0 V mA 20 80 150 gm Transconductance, VDS = 2.0 V, ID = 14 mA mS 70 85
VGS(off) Gate to Source Cutoff Voltage, VDS = 2.0 V, ID = 100 ??, V -0.2 -0.9 -2.5
IGSO Gate to Source Leak Current, VGS = -3.0 V ?? 0.5 10
1. Typical values of noise figures and associated gain are those obtained when 50% of the devices from a large number of lots were individually measured in a circuit with the input individually tuned to obtain the minimum value. Maximum values are criteria established on the production line as a "go-no-go" screening tuned for the "generic" type but not each specimen.
California Eastern Laboratories
ABSOLUTE MAXIMUM RATINGS1 (TA = 25??)
SYMBOLS PARAMETERS UNITS RATINGS
VDS Drain to Source Voltage V 4.0
VGS Gate to Source Voltage V -3.0
IDS Drain Current mA IDSS
TCH Channel Temperature ?? 125
TSTG Storage Temperature ?? -65 to +125
PT Total Power Dissipation mW 300
1. Operation in excess of any one of these conditions may result in permanent damage.
TYPICAL NOISE PARAMETERS (TA = 25??)
VDS = 2 V, IDS = 15 mA
FREQ. NFMIN GA ??PT
(GHz) (dB) (dB) MAG ANG Rn/50
2 0.23 17.0 0.77 15 0.19
4 0.25 16.0 0.58 43 0.18
6 0.28 14.7 0.43 82 0.13
8 0.31 13.6 0.32 127 0.08
10 0.38 12.5 0.27 175 0.07
12 0.48 11.5 0.27 -139 0.10
14 0.60 10.5 0.34 -100 0.17
16 0.73 9.6 0.48 -70 0.29
18 0.88 8.8 0.69 -56 0.46
TYPICAL PERFORMANCE CURVES (TA = 25??)
TYPICAL CONSTANT NOISE FIGURE CIRCLE (VDS = 2 V, IDS = 15 mA, f = 4 GHz)
TOTAL POWER DISSIPATION vs.
AMBIENT TEMPERATURE
0 50 100 150 200 250
Ambient Temperature, TA (??)
0.4 dB
DRAIN CURRENT vs. GATE TO SOURCE VOLTAGE
VDS = 2 V
DRAIN CURRENT vs. DRAIN TO SOURCE VOLTAGE
VGS = 0 V
-2.0 -1.0 0
0 1 2 3 4 5
Gate to Source Voltage, VGS (V)
Drain to Source Voltage, VDS (V)
TYPICAL COMMON SOURCE SCATTERING PARAMETERS (TA = 25??)
Coordinates in Ohms Frequency in GHz VDS = 2 V, ID = 10 mA
VDS = 2 V, ID = 10 mA
FREQUENCY S11 S21 S12 S22 K MAG1
(GHz) MAG ANG MAG ANG MAG ANG MAG ANG (dB)
0.1 1.002 -2.0 5.985 177.7 0.002 96.6 0.538 -1.3 -0.17 34.5
0.5 0.996 -9.7 5.938 170.3 0.013 84.0 0.535 -7.5 0.06 26.7
1.0 0.981 -19.2 5.855 160.9 0.025 77.2 0.529 -15.1 0.14 23.7
1.5 0.960 -28.6 5.765 151.7 0.036 71.1 0.518 -22.4 0.21 22.0
2.0 0.933 -38.0 5.671 142.7 0.048 65.5 0.504 -29.9 0.26 20.8
2.5 0.903 -47.4 5.554 133.9 0.058 59.6 0.488 -37.0 0.32 19.8
3.0 0.869 -57.0 5.429 125.1 0.068 53.6 0.467 -44.3 0.37 19.0
3.5 0.829 -66.6 5.279 116.5 0.078 48.3 0.445 -51.5 0.43 18.3
4.0 0.788 -76.5 5.126 108.0 0.086 42.5 0.420 -58.3 0.49 17.7
4.5 0.746 -86.5 4.954 99.4 0.094 37.3 0.394 -65.9 0.54 17.2
5.0 0.702 -96.7 4.773 91.2 0.100 32.3 0.366 -73.2 0.60 16.8
5.5 0.662 -107.1 4.593 83.2 0.106 27.5 0.339 -81.0 0.65 16.4
6.0 0.625 -117.7 4.421 75.5 0.111 22.5 0.309 -88.6 0.70 16.0
6.5 0.594 -128.4 4.232 67.9 0.115 17.5 0.282 -96.4 0.75 15.7
7.0 0.566 -139.1 4.059 60.5 0.119 13.2 0.257 -104.5 0.79 15.3
7.5 0.545 -149.9 3.886 53.2 0.121 9.2 0.234 -112.8 0.84 15.1
8.0 0.528 -160.6 3.720 46.2 0.123 4.7 0.210 -121.7 0.88 14.8
8.5 0.514 -170.7 3.567 39.3 0.126 1.2 0.190 -129.4 0.92 14.5
9.0 0.511 179.1 3.426 32.5 0.128 -2.7 0.172 -139.7 0.95 14.3
9.5 0.510 168.8 3.292 25.8 0.129 -6.7 0.154 -150.9 0.98 14.1
10.0 0.514 158.8 3.151 19.0 0.131 -10.8 0.142 -164.7 1.01 13.2
10.5 0.521 148.9 3.021 12.5 0.132 -14.2 0.132 177.8 1.04 12.4
11.0 0.532 139.2 2.894 6.3 0.131 -17.9 0.122 158.9 1.08 11.7
11.5 0.543 131.0 2.764 0.2 0.132 -21.8 0.125 143.5 1.11 11.2
12.0 0.562 123.0 2.654 -6.0 0.132 -25.0 0.138 128.5 1.12 10.9
12.5 0.580 115.5 2.544 -12.2 0.131 -28.8 0.153 115.5 1.14 10.6
TYPICAL COMMON SOURCE SCATTERING PARAMETERS (TA = 25??)
Coordinates in Ohms Frequency in GHz VDS = 2 V, ID = 15 mA
VDS = 2 V, ID = 15 mA
FREQUENCY S11 S21 S12 S22 K MAG1
(GHz) MAG ANG MAG ANG MAG ANG MAG ANG (dB)
2.0 .998 -41.7 7.162 140.1 .042 68.4 .415 -27.5 .10 41.82
2.5 .927 -47.5 6.856 133.6 .050 65.9 .479 -35.8 .23 26.36
3.0 .860 -61.3 6.603 122.0 .057 57.5 .423 -43.0 .39 23.09
3.5 .829 -69.9 6.305 114.4 .064 54.1 .429 -47.9 .42 21.91
4.0 .802 -79.2 6.033 106.8 .071 49.6 .426 -51.7 .45 20.95
4.5 .716 -87.5 5.687 98.5 .075 45.8 .406 -56.2 .60 19.00
5.0 .659 -93.9 5.415 91.6 .081 41.1 .394 -59.7 .69 17.88
5.5 .601 -99.7 5.184 84.7 .085 38.9 .374 -63.3 .78 16.89
6.0 .592 -108.5 5.050 77.6 .091 35.2 .340 -68.1 .79 16.47
6.5 .550 -118.5 4.912 70.5 .096 30.8 .311 -73.0 .84 15.83
7.0 .514 -130.2 4.774 63.0 .102 27.3 .279 -79.1 .87 15.26
7.5 .488 -144.5 4.600 55.4 .107 22.0 .232 -87.5 .91 14.68
8.0 .464 -158.9 4.401 47.9 .109 18.6 .189 -97.7 .96 14.08
8.5 .463 -171.7 4.187 41.0 .113 14.9 .155 -109.3 .98 13.59
9.0 .468 176.6 3.997 34.1 .114 11.5 .134 -126.9 1.00 15.01
9.5 .472 166.4 3.812 27.7 .118 7.7 .121 -142.8 1.02 14.21
10.0 .472 156.2 3.628 21.5 .119 4.7 .111 -156.2 1.06 13.37
10.5 .476 147.0 3.477 15.6 .122 1.0 .103 -170.1 1.08 12.86
11.0 .476 137.8 3.351 9.6 .124 -2.5 .098 174.4 1.10 12.36
11.5 .488 127.7 3.251 3.5 .125 -5.8 .093 157.9 1.12 12.06
12.0 .518 118.1 3.150 -2.9 .128 -9.2 .105 137.6 1.10 11.98
12.5 .552 109.6 3.036 -9.7 .130 -12.9 .131 121.0 1.08 11.92
13.0 .593 101.9 2.875 -16.4 .131 -16.7 .177 107.0 1.07 11.79
13.5 .635 95.2 2.714 -22.7 .129 -21.2 .223 97.8 1.06 11.70
14.0 .661 90.1 2.546 -28.1 .126 -22.5 .259 91.0 1.08 11.29
14.5 .688 86.1 2.418 -32.6 .124 -24.9 .284 87.0 1.08 11.17
15.0 .707 82.2 2.327 -37.0 .127 -27.4 .316 86.0 1.05 11.30
15.5 .719 79.7 2.240 -41.8 .126 -28.8 .332 83.3 1.04 11.20
16.0 .730 76.1 2.168 -46.8 .129 -31.6 .352 81.7 1.01 11.55
16.5 .752 71.3 2.100 -52.7 .131 -33.2 .380 77.4 .98 10.74
17.0 .771 65.5 2.021 -58.4 .130 -38.5 .398 72.4 .96 10.78
17.5 .803 60.4 1.930 -65.1 .134 -42.2 .422 66.5 .89 11.05
18.0 .817 55.7 1.814 -70.5 .128 -44.3 .445 62.9 .91 10.92
1. Gain Calculations:
MAG = |S21|
K 2 - 1 ). When K ??1, MAG is undefined and MSG values are used. MSG = |S21|
, K = 1 + | ??€? - |S11| - |S22| , ??= S11 S22 - S21 S12
2 |S12 S21|
MAG = Maximum Available Gain
MSG = Maximum Stable Gain
TYPICAL COMMON SOURCE SCATTERING PARAMETERS (TA = 25??)
Coordinates in Ohms Frequency in GHz VDS = 2 V, ID = 20 mA
VDS = 2 V, ID = 20 mA
FREQUENCY S11 S21 S12 S22 K MAG1
(GHz) MAG ANG MAG ANG MAG ANG MAG ANG (dB)
0.1 1.002 -2.2 7.768 177.7 0.003 83.5 0.439 -1.4 -0.01 33.9
0.5 0.994 -10.7 7.685 169.3 0.011 85.2 0.436 -7.7 0.08 28.4
1.0 0.974 -21.3 7.530 159.0 0.022 77.5 0.430 -15.5 0.18 25.3
1.5 0.946 -31.7 7.350 149.1 0.033 71.7 0.419 -23.1 0.26 23.5
2.0 0.911 -41.9 7.155 139.5 0.042 66.3 0.405 -30.5 0.33 22.3
2.5 0.870 -52.0 6.927 130.1 0.051 61.3 0.388 -37.8 0.40 21.3
3.0 0.826 -62.2 6.682 121.0 0.060 55.8 0.367 -45.0 0.47 20.5
3.5 0.780 -72.4 6.418 112.1 0.068 50.5 0.346 -52.1 0.53 19.7
4.0 0.733 -82.6 6.152 103.5 0.076 45.6 0.322 -58.7 0.60 19.1
4.5 0.685 -93.1 5.871 95.0 0.083 40.9 0.298 -66.3 0.65 18.5
5.0 0.640 -103.6 5.592 86.9 0.088 36.3 0.272 -73.5 0.71 18.0
5.5 0.599 -114.3 5.326 79.1 0.094 31.9 0.248 -81.3 0.76 17.6
6.0 0.565 -125.1 5.077 71.6 0.099 27.7 0.222 -89.0 0.81 17.1
6.5 0.536 -136.0 4.822 64.3 0.103 23.8 0.198 -97.3 0.85 16.7
7.0 0.512 -146.9 4.595 57.2 0.107 19.5 0.176 -106.2 0.90 16.3
7.5 0.496 -157.8 4.375 50.2 0.111 16.0 0.156 -115.6 0.93 16.0
8.0 0.483 -168.6 4.166 43.5 0.113 11.8 0.138 -126.3 0.97 15.7
8.5 0.473 -178.5 3.979 37.0 0.117 8.6 0.120 -135.8 1.00 15.3
9.0 0.475 171.5 3.807 30.4 0.120 5.0 0.107 -149.5 1.02 14.2
9.5 0.478 161.6 3.644 24.0 0.123 1.2 0.096 -165.3 1.04 13.5
10.0 0.487 152.0 3.479 17.6 0.125 -2.9 0.092 175.2 1.06 13.0
10.5 0.498 142.5 3.327 11.4 0.128 -6.2 0.097 152.5 1.07 12.5
11.0 0.514 133.3 3.181 5.4 0.128 -9.7 0.103 130.1 1.10 12.0
11.5 0.527 125.6 3.036 -0.4 0.130 -13.7 0.116 116.5 1.11 11.6
12.0 0.548 118.1 2.911 -6.4 0.131 -17.1 0.137 104.9 1.12 11.4
12.5 0.569 111.1 2.789 -12.3 0.132 -21.0 0.160 95.2 1.13 11.1
OUTLINE DIMENSIONS (Units in mm)
PACKAGE OUTLINE S01
2.0 ??0.2
ORDERING INFORMATION
PART NUMBER AVAILABILITY PACKAGE
NE334S01 Bulk S01
NE334S01-T1 Tape & reel 1K/reel S01
NE334S01-T1B Tape & reel 4K/reel S01
0.65 TYP.
1.9 ??0.2
1. Source
2. Drain
3. Source
4. Gate
0.125 ??0.05
0.4 MAX
4.0 ??0.2
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ADP3120A price
ADP3120A pinout
ADP3120A transistor
Dual Bootstrapped, 12 V MOSFET Driver with Output Disable
ADP3120A
FEATURES
All-in-one synchronous buck driver
Bootstrapped high-side drive
One PWM signal generates both drives Anticross conduction protection circuitry OD for disabling the driver outputs
Meets CPU VR requirement when used with
Analog Devices Flex -Mode??1 controller
APPLICATIONS
Multiphase desktop CPU supplies
Single-supply synchronous buck converters
GENERAL DESCRIPTION
The ADP3120A is a dual, high voltage MOSFET driver optimized for driving two N-channel MOSFETs, the two switches in a nonisolated synchronous buck power converter. Each
driver is capable of driving a 3000 pF load with a 45 ns propaga- tion delay and a 25 ns transition time. One of the drivers can be bootstrapped and is designed to handle the high voltage slew rate associated with floating high-side gate drivers. The ADP3120A includes overlapping drive protection to prevent shoot-through current in the external MOSFETs.
The OD pin shuts off both the high-side and the low-side MOSFETs to prevent rapid output capacitor discharge during system shutdown.
The ADP3120A is specified over the commercial temperature range of 0?C to 85?C and is available in 8-lead SOIC_N and
8-lead LFCSP_VD packages.
1 Flex-Mode is protected by U.S. Patent 6683441; other patents pending.
FUNCTIONAL BLOCK DIAGRAM
ADP3120A
LATCH R1
CONTROL LOGIC
Figure 1.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of thirdparties that may result from its use. Specifications subject tochange without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks andregisteredtrademarks arethe propertyoftheir respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ?2006 Analog Devices, Inc. All rights reserved.
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Pin Configurations and Function Descriptions ........................... 5
Timing Characteristics..................................................................... 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ........................................................................ 9
Low-Side Driver ............................................................................9
High-Side Driver ...........................................................................9
Overlap Protection Circuit...........................................................9
Application Information................................................................ 10
Supply Capacitor Selection ....................................................... 10
Bootstrap Circuit ........................................................................ 10
MOSFET Selection..................................................................... 10
High-Side (Control) MOSFETs ................................................ 10
Low-Side (Synchronous) MOSFETs ........................................ 11
PC Board Layout Considerations............................................. 11
Outline Dimensions ....................................................................... 13
Ordering Guide .......................................................................... 13
REVISION HISTORY
3/06??evision 0: Initial Version
SPECIFICATIONS
VCC = 12 V, BST = 4 V to 26 V, TA = 0?C to 85?C, unless otherwise noted. 1
Table 1.
Parameter
Symbol
Conditions
Min Typ Max
DIGITAL INPUTS (PWM, OD) Input Voltage High
Input Voltage Low
Input Current
Hysteresis
90 250
V V ?A mV
HIGH-SIDE DRIVER
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Output Resistance, Unbiased
Transition Times
Propagation Delay Times
SW Pull-Down Resistance
trDRVH tfDRVH tpdhDRVH
tpdlDRVH t pdlOD tpdhOD
BST ??SW = 12 V ; TA = 25?C
BST ??SW = 12 V ; TA = 0?C to 85?C BST ??SW = 12 V; TA = 25?C
BST ??SW = 12 V; TA = 0?C to 85?C BST ??SW = 0 V
BST ??SW = 12 V, CLOAD = 3 nF, see Figure 5
BST ??SW = 12 V, CLOAD = 3 nF, see Figure 5
BST ??SW = 12 V, CLOAD = 3 nF,
25?C ??TA ??85?C, see Figure 5
BST ??SW = 12 V, CLOAD = 3 nF, see Figure 5
See Figure 4
See Figure 4
SW to PGND
2.5 3.9
1.4 2.6
32 45 70
? ? ? ? k? ns ns ns
LOW-SIDE DRIVER
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Output Resistance, Unbiased
Transition Times
Propagation Delay Times
Timeout Delay
trDRVL tfDRVL tpdhDRVL tpdlDRVL
t pdl OD
TA = 25?C
TA = 0?C to 85?C TA = 25?C
TA = 0?C to 85?C VCC = PGND
CLOAD = 3 nF, see Figure 5
CLOAD = 3 nF, see Figure 5
CLOAD = 3 nF, see Figure 5
CLOAD = 3 nF, see Figure 5
See Figure 4
See Figure 4
SW = 5 V
SW = PGND
2.4 3.9
1.4 2.6
110 190
110 190
95 150
? ? ? ? k? ns ns ns ns ns
SUPPLY
Supply Voltage Range
Supply Current UVLO Voltage Hysteresis
BST = 12 V, IN = 0 V VCC rising
4.15 13.2
1.5 3.0
V mA V mV
1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods.
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
VCC ??.3 V to +15 V BST
DC ??.3 V to VCC + 15 V
<200 ns ??.3 V to +35 V BST to SW ??.3 V to +15 V SW
DC ?? V to +15 V
<200 ns ??0 V to +25 V DRVH
DC SW ??0.3 V to BST + 0.3 V
<200 ns SW ??2 V to BST + 0.3 V DRVL
DC ??.3 V to VCC + 0.3 V
<200 ns ?? V to VCC + 0.3 V IN, OD ??.3 V to +6.5 V ?JA, SOIC_N
2-Layer Board 123?C/W
4-Layer Board 90?C/W
?JA, LFCSP_VD1
4-Layer Board 50?C/W
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Unless otherwise specified, all voltages are referenced to PGND.
Operating Ambient Temperature
0?C to 85?C
Junction Temperature Range 0?C to 150?C Storage Temperature Range ??5?C to +150?C Lead Temperature
Soldering (10 sec) 300?C Vapor Phase (60 sec) 215?C Infrared (15 sec) 260?C
1 For LFCSP_VD, ?JA is measured per JEDEC STD with exposed pad soldered to PCB.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
BST 1
8 DRVH
7 SW PGND DRVL
INDICATOR
ADP3120A TOP VIEW (Not to Scale)
8 DRVH
6 PGND
5 DRVL
Figure 2. 8-Lead SOIC_N Pin Configuration
Figure 3. 8-Lead LFCSP_VD Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
BST IN
OD VCC DRVL PGND SW
Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds this bootstrapped voltage for the high-side MOSFET while it is switching.
Logic Level PWM Input. This pin has primary control of the drive outputs. In normal operation, pulling this pin low turns on the low-side driver; pulling it high turns on the high-side driver.
Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low. Input Supply. This pin should be bypassed to PGND with an ~1 ?F ceramic capacitor. Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET. Power Ground. This pin should be closely connected to the source of the lower MOSFET.
Switch Node Connection. This pin is connected to the buck switching node, close to the upper MOSFET source. It is the floating return for the upper MOSFET drive signal. It is also used to monitor the switched voltage to prevent the lower MOSFET from turning on until the voltage is below ~1 V.
Buck Drive. Output drive for the upper (buck) MOSFET.
TIMING CHARACTERISTICS
Timing is referenced to the 90% and 10% points, unless otherwise noted.
tpdhOD
DRVH OR DRVL
Figure 4. Output Disable Timing Diagram
tpdlDRVL tfDRVL
tpdlDRVH trDRVL
tpdhDRVH trDRVH
tfDRVH
DRVH-SW
VTH VTH
tpdhDRVL
Figure 5. Timing Diagram
TYPICAL PERFORMANCE CHARACTERISTICS
VCC = 12V CLOAD = 3nF
0 25 50 75 100
JUNCTION TEMPERATURE (?C)
Figure 6. DRVH Rise and DRVL Fall Times
CLOAD = 6 nF for DRVL, CLOAD = 2 nF for DRVH
Figure 9. DRVH and DRVL Fall Times vs. Temperature
TA = 25?C VCC = 12V
35 DRVH
2.5 3.0 3.5 4.0 4.5
LOAD CAPACITANCE (nF)
Figure 7. DRVH Fall and DRVL Rise Times
CLOAD = 6 nF for DRVL, CLOAD = 2 nF for DRVH
Figure 10. DRVH and DRVL Rise Times vs. Load Capacitance
VCC = 12V CLOAD = 3nF
VCC = 12V TA = 25?C
0 25 50 75 100
JUNCTION TEMPERATURE (?C)
2.5 3.0 3.5 4.0 4.5
LOAD CAPACITANCE (nF)
Figure 8. DRVH and DRVL Rise Times vs. Temperature
Figure 11. DRVH and DRVL Fall Times vs. Load Capacitance
TA= 25?C 11
VCC = 12V
CLOAD = 3nF 10
0 200 400 600 800 1000 1200 1400
FREQUENCY (kHz)
Figure 12. Supply Current vs. Frequency
0 1 2 3 4 5 6 7 8 9 10 11 12
VCC (V)
Figure 14. DRVL Output Voltage vs. Supply Voltage
VCC = 12V CLOAD = 3nF fIN = 250kHz
0 25 50 75 100
JUNCTION TEMPERATURE (?C)
Figure 13. Supply Current vs. Temperature
THEORY OF OPERATION
The ADP3120A is optimized for driving two N-channel MOSFETs in a synchronous buck converter topology. A single PWM input signal is all that is required to properly drive the high-side and the low-side MOSFETs. Each driver is capable of driving a 3 nF load at speeds up to 500 kHz. A functional block diagram of ADP3120A is shown in Figure 1.
LOW-SIDE DRIVER
The low-side driver is designed to drive a ground referenced N-channel MOSFET. The bias to the low-side driver is internally connected to the VCC supply and PGND.
When the driver is enabled, the driver output is 180? out of phase with the PWM input. When the ADP3120A is disabled, the low-side gate is held low.
HIGH-SIDE DRIVER
The high-side driver is designed to drive a floating N-channel MOSFET. The bias voltage for the high-side driver is developed by an external bootstrap supply circuit that is connected between the BST and SW pins.
The bootstrap circuit comprises Diode D1 and Bootstrap Capacitor CBST1. CBST2 and RBST are included to reduce the high- side gate drive voltage and to limit the switch node slew rate (called a Boot-Snap??circuit??ee the Application Information section for more details). When the ADP3120A starts up, the SW pin is at ground, so the bootstrap capacitor charges up to VCC through D1. When the PWM input goes high, the high-side driver begins to turn on the high-side MOSFET, Q1, by pulling charge out of CBST1 and CBST2. As Q1 turns on, the SW pin rises up to VIN and forces the BST pin to VIN + VC (BST). This holds Q1
on because enough gate-to-source voltage is provided. To complete the cycle, Q1 is switched off by pulling the gate down to the voltage at the SW pin. When the low-side MOSFET, Q2, turns on, the SW pin is pulled to ground. This allows the bootstrap capacitor to charge up to VCC again.
The output of the high-side driver is in phase with the PWM
input. When the driver is disabled, the high-side gate is held low.
OVERLAP PROTECTION CIRCUIT
The overlap protection circuit prevents both of the main power switches, Q1 and Q2, from being on at the same time. This is done to prevent shoot-through currents from flowing through both power switches and the associated losses that can occur during their on/off transitions. The overlap protection circuit accomplishes this by adaptively controlling the delay from the Q1 turn-off to the Q2 turn-on, and by internally setting the delay from the Q2 turn-off to the Q1 turn-on.
To prevent the overlap of the gate drives during the Q1 turn-off and the Q2 turn-on, the overlap circuit monitors the voltage at the SW pin. When the PWM input signal goes low, Q1 begins
to turn off (after propagation delay). Before Q2 can turn on, the overlap protection circuit makes sure that SW has first gone high and then waits for the voltage at the SW pin to fall from
VIN to 1 V. Once the voltage on the SW pin falls to 1 V, Q2 begins turn-on. If the SW pin has not gone high first, the Q2 turn-on is delayed by a fixed 150 ns. By waiting for the voltage on the SW pin to reach 1 V or for the fixed delay time, the overlap protection circuit ensures that Q1 is off before Q2 turns on, regardless of variations in temperature, supply voltage, input pulse width, gate charge, and drive current. If SW does not go below 1 V after 190 ns, DRVL turns on. This can occur if the current flowing in the output inductor is negative and flows through the high-side MOSFET body diode.
APPLICATION INFORMATION
SUPPLY CAPACITOR SELECTION
For the supply input (VCC) of the ADP3120A, a local bypass capacitor is recommended to reduce the noise and to supply some of the peak currents that are drawn. Use a 4.7 ?F, low ESR capacitor. Multilayer ceramic chip (MLCC) capacitors provide
A small signal diode can be used for the bootstrap diode due to the ample gate drive voltage supplied by VCC. The bootstrap diode must have a minimum 15 V rating to withstand the maximum supply voltage. The average forward current can
be estimated by
the best combination of low ESR and small size. Keep the ceramic capacitor as close as possible to the ADP3120A.
BOOTSTRAP CIRCUIT
The bootstrap circuit uses a charge storage capacitor (CBST)
and a diode, as shown in Figure 1. These components can be
I F ( AVG) = QGATE ? f MAX
where fMAX is the maximum switching frequency of the controller.
The peak surge current rating should be calculated by
selected after the high-side MOSFET is chosen. The bootstrap
V ??V
capacitor must have a voltage rating that can handle twice the maximum supply voltage. A minimum 50 V rating is
I F ( PEAK ) =
CC D
recommended. The capacitor values are determined by
MOSFET SELECTION
+ C BST2
= 10 ? QGATE
When interfacing the ADP3120A to external MOSFETs, the designer should consider ways to make a robust design that
C BST1 + CBST2
= VGATE
VCC ??VD
minimizes stresses on both the driver and the MOSFETs. These
stresses include exceeding the short time duration voltage ratings on the driver pins as well as the external MOSFET.
QGATE is the total gate charge of the high-side MOSFET at VGATE.
VGATE is the desired gate drive voltage (usually in the range of
5 V to 10 V, 7 V being typical).
VD is the voltage drop across D1.
Rearranging Equation 1 and Equation 2 to solve for CBST1 yields
It is also highly recommended to use the Boot-Snap circuit to improve the interaction of the driver with the characteristics of the MOSFETs. If a simple bootstrap arrangement is used, make sure to include a proper snubber network on the SW node.
HIGH-SIDE (CONTROL) MOSFETS
C = 10 ?
A high-side, high speed MOSFET is usually selected to
minimize switching losses (see the ADP3186 or ADP3188
CBST2 can then be found by rearranging Equation 1
data sheet for Flex-Mode controller details). This typically implies a low gate resistance and low input capacitance/charge
? QGATE ??C BST 1
device. Yet, a significant source lead inductance can also exist that depends mainly on the MOSFET package; it is best to
contact the MOSFET vendor for this information.
For example, an NTD60N02 has a total gate charge of about
12 nC at VGATE = 7 V. Using VCC = 12 V and VD = 1 V, then
CBST1 = 12 nF and CBST2 = 6.8 nF. Good quality ceramic capacitors should be used.
RBST is used to limit slew rate and minimize ringing at the switch node. It also provides peak current limiting through D1. An
RBST value of 1.5 ? to 2.2 ? is a good choice. The resistor needs to handle at least 250 mW due to the peak currents that flow
through it.
The ADP3120A DRVH output impedance and the input resistance of the MOSFETs determine the rate of charge delivery to the internal capacitance of the gate. This determines the
speed at which the MOSFETs turn on and off. However, because of potentially large currents flowing in the MOSFETs at the on and off times (this current is usually larger at turn-off due to ramping up of the output current in the output inductor), the source lead inductance generates a significant voltage when the high-side MOSFETs switch off. This creates a significant drain- source voltage spike across the internal die of the MOSFETs and can lead to a catastrophic avalanche. The mechanisms involved in this avalanche condition are referenced in literature from the MOSFET suppliers.
The MOSFET vendor should provide a rating for the maximum voltage slew rate at drain current around which this can be designed. Once this specification is obtained, determine the maximum current expected in the MOSFET by
monitored to go below one sixth of VCC; then, a delay is added. Due to the Miller capacitance and internal delays of the low- side MOSFET gate, ensure that the Miller-to-input capacitance ratio is low enough, and that the low-side MOSFET internal
( per phase) + (V
??VOUT ) ?
delays are not so large as to allow accidental turn-on of the low-
side when the high-side turns on.
Contact ADI for an updated list of recommended low-side
DMAX is determined for the VR controller being used with
the driver. This current is divided roughly equally between MOSFETs if more than one is used (assume a worst-case mismatch of 30% for design margin).
LOUT is the output inductor value.
When producing the design, there is no exact method for calculating the dV/dt due to the parasitic effects in the external MOSFETs as well as the PCB. However, it can be measured to determine if it is safe. If it appears that the dV/dt is too fast, an optional gate resistor can be added between DRVH and the high-side MOSFETs. This resistor slows down the dV/dt, but it increases the switching losses in the high-side MOSFETs. The ADP3120A is optimally designed with an internal drive impedance that works with most MOSFETs to switch them efficiently, yet minimizes dV/dt. However, some high speed MOSFETs can require this external gate resistor depending on the currents being switched in the MOSFET.
LOW-SIDE (SYNCHRONOUS) MOSFETS
The low-side MOSFETs are usually selected to have a low on resistance to minimize conduction losses. This usually implies a large input gate capacitance and gate charge. The first concern is to make sure the power delivery from the ADP3120A DRVL does not exceed the thermal rating of the driver (see the ADP3186, ADP3188, or ADP3189 data sheets for Flex-Mode controller details).
MOSFETs.
PC BOARD LAYOUT CONSIDERATIONS
Use these general guidelines when designing printed circuit boards:
??Trace out the high current paths and use short, wide
(>20 mil) traces to make these connections.
??Minimize trace inductance between DRVH and DRVL
outputs and MOSFET gates.
??Connect the PGND pin of the ADP3120A as closely as possible to the source of the lower MOSFET.
??Locate the VCC bypass capacitor as close as possible to the VCC and PGND pins.
??Use vias to other layers, when possible, to maximize thermal conduction away from the IC.
The circuit in Figure 16 shows how four drivers can be combined with an ADP3188 to form a total power conver- sion solution for generating VCC (CORE) for an Intel CPU that is VRD 10.x-compliant.
Figure 15 shows an example of the typical land patterns based on the guidelines given previously. For more detailed layout guidelines for a complete CPU voltage regulator subsystem, refer to the PC Board Layout Considerations section of the ADP3188 data sheet.
The next concern for the low-side MOSFETs is to prevent
them from being inadvertently switched on when the high-side MOSFET turns on. This occurs due to the drain-gate (Miller capacitance, also specified as Crss capacitance) of the MOSFET. When the drain of the low-side MOSFET is switched to VCC by the high-side turning on (at a dV/dt rate), the internal gate of the low-side MOSFET is pulled up by an amount roughly equal
to VCC ? (Crss/Ciss). It is important to make sure this does not put the MOSFET into conduction.
Another consideration is the nonoverlap circuitry of the ADP3120A that attempts to minimize the nonoverlap period. During the state of the high-side turning off to low-side turning on, the SW pin is monitored (as well as the conditions of SW prior to switching) to adequately prevent overlap.
However, during the low-side turn-off to high-side turn-on, the SW pin does not contain information for determining the proper switching time, so the state of the DRVL pin is
Figure 15. External Component Placement Example
18A 2700?F/16V/3.3A ? 2
SANYO MV-WX SERIES
+ + 4.7?F
VIN RTN
ADP3120A 6.8nF
1 BST
DRVH 8
NTD60N02 L2
560?F/4V ? 8
VCC (CORE)
2 IN
SW 7
320nH/1.4m? SANYO SEPC SERIES
0.8375V ??1.6V
3 OD
4 VCC
PGND 6
DRVL 5
NTD110N02
NTD110N02
5m? EACH
+ + C24 C31
95A TDC, 119A PK
VCC (CORE) RTN
10?F ? 18
MLCC IN SOCKET
ADP3120A 6.8nF
1 BST
2 IN
3 OD
4 VCC
DRVH 8
PGND 6
DRVL 5
NTD110N02
NTD60N02
NTD110N02
320nH/1.4m?
357k?, ADP3188
1 VID4
VCC 28
U4 C14
2 VID3
PWM1 27
ADP3120A 6.8nF
FROM CPU
3 VID2
4 VID1
5 VID0
6 VID5
PWM2 26
PWM3 25
PWM4 24
SW1 23
1 BST
2 IN
3 OD
4 VCC
DRVH 8
PGND 6
DRVL 5
NTD60N02
320nH/1.4m?
7 FBRTN
SW2 22
R 1
RA 22pF
8 FB
9 COMP
SW3 21
SW4 20
NTD110N02
NTD110N02
1.21k? 470pF 12.1k?
10 PWRGD
GND 19
158k?, 1%
RPH3 158k?,
11 EN
12 DELAY
CSCOMP 18
CSSUM 17
158k?,
1% 158k?,
RLDY RT
13 RT
CSREF 16
35.7k? 84.5k?
U5 C186.8nF
ADP3120A
137k?,
14 RAMPADJ ILIMIT 15
1 BST
2 IN
3 OD
4 VCC
DRVH 8
PGND 6
DRVL 5
NTD60N02
320nH/1.4m?
100k?, 5% NTC
NTD110N02
NTD110N02
1FOR A DESCRIPTION OF OPTIONAL COMPONENTS, SEE THE ADP3188 THEORY OF OPERATION SECTION.
05812-016
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
6.20 (0.2440)
3.80 (0.1497) 1
4 5.80 (0.2284)
0.25 (0.0098)
0.10 (0.0040)
1.27 (0.0500) BSC
1.75 (0.0688)
1.35 (0.0532)
0.50 (0.0196) ? 45?
0.25 (0.0099)
COPLANARITY
SEATING PLANE
0.51 (0.0201)
0.31 (0.0122)
0.25 (0.0098) 0?
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 17. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body
Dimensions shown in millimeters and (inches)
3.00 BSC SQ
0.60 MAX
INDICATOR
INDICATOR
TOP VIEW
BSC 5
0.90 MAX
0.85 NOM
SEATING PLANE
12? MAX 0.70 MAX
0.65 TYP
0.05 MAX
0.01 NOM
0.20 REF
Figure 18. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]
3 mm x 3 mm Body, Very Thin, Dual Lead
(CP-8-2)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Package Description
Package
Ordering
Quantity
Branding
ADP3120AJRZ1
ADP3120AJRZ-RL1
ADP3120AJCPZ-RL1
0?C to 85?C
0?C to 85?C
0?C to 85?C
8-Lead Standard Small Outline Package (SOIC_N)
8-Lead Standard Small Outline Package (SOIC_N)
8-Lead Lead Frame Chip Scale Package (LFCSP_VD)
1 Z = Pb-free part.
?2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
D05812-0-3/06(0)
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[url=http://www.utsource.net/2MBI75S-120.html]2MBI75S-120[/url] T-13/4 (5 mm) Diffused LED Lamps
IGBT MODULE ( S-Series )
??Features
??NPT-Technology
??Square SC SOA at 10 x IC
??High Short Circuit Withstand-Capability
??Small Temperature Dependence of the Turn-Off
Switching Loss
??Low Losses And Soft Switching
??Applications
??High Power Switching
??A.C. Motor Controls
??D.C. Motor Controls
??Uninterruptible Power Supply
??Outline Drawing
??Maximum Ratings and Characteristics ??Equivalent Circuit
??Absolute Maximum Ratings ( Tc=25?C)
Symbols
Ratings
Collector-Emitter Voltage
Gate -Emitter Voltage
Collector
Current
Continuous
25?C / 80?C
100 / 75
25?C / 80?C
IC PULSE
200 / 150
Continuous
-IC PULSE
Max. Power Dissipation
Operating Temperature
Storage Temperature
-40 ??+125
Isolation Voltage
A.C. 1min.
Screw Torque
Mounting *2
Terminals *2
Note: 1*: All Terminals should be connected together when isolation test will be done.
2*: Recommendable Value; 2.5 ??3.5 Nm (M5)
??Electrical Characteristics ( at Tj=25?C )
Symbols
Test Conditions
Zero Gate Voltage Collector Current
VGE=0V VCE=1200V
Gate-Emitter Leackage Current
VCE=0V VGE=? 20V
Gate-Emitter Threshold Voltage
VGE(th)
VGE=20V IC=75mA
Collector-Emitter Saturation Voltage
VCE(sat)
VGE=15V IC=75A
Tj = 25?C
Tj =125?C
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
VGE=0V VCE=10V f=1MHz
Turn-on Time
VCC = 600V IC = 75A
VGE = ?15V RG = 16??Inductive Load
Turn-off Time
Diode Forward On-Voltage
IF=75A; VGE=0V
Tj = 25?C
Tj =125?C
Reverse Recovery Time
IF=75A
??Thermal Characteristics
Symbols
Test Conditions
Thermal Resistance
Rth(j-c)
Rth(j-c)
Rth(c-f)
With Thermal Compound
Specification is subject to change without notice September 2000
[url=http://www.utsource.net/2MBI75S-120.html]http://www.utsource.net/2MBI75S-120.html[/url]
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[url=http://www.utsource.net/2N4113.html]2N4113[/url] T-13/4 (5 mm) Diffused LED Lamps
Dimensions in mm (inches).
25.15 (0.99)
26.67 (1.05)
10.67 (0.42)
11.18 (0.44)
1.52 (0.06)
3.43 (0.135)
6.35 (0.25)
9.15 (0.36)
Bipolar NPN Device in a
Hermetically sealed TO3
Metal Package.
3 (case)
Bipolar NPN Device.
VCEO = 80V
3.84 (0.151)
4.09 (0.161)
TO3 (TO204AA) PINOUTS
7.92 (0.312)
12.70 (0.50)
IC = 5A
All Semelab hermetically sealed products can be processed in accordance with the requirements of BS, CECC and JAN, JANTX, JANTXV and JANS specifications.
1 ??Base 2 ??Emitter Case - Collector
Parameter Test Conditions Min. Typ. Max. Units VCEO* 80 V IC(CONT) 5 A
hFE @ 5/2 (VCE / IC) 40 120 -
ft 50M Hz
PD 30 W
* Maximum Working Voltage
This is a shortform datasheet. For a full datasheet please contact .
Semelab Plc reserves the right to change test conditions, parameter limits and package dimensions without notice. Information furnished by Semelab is believed to be both accurate and reliable at the time of going to press. However Semelab assumes no responsibility for any errors or omissions discovered in its use.
Semelab plc. Telephone +44(0)1455 556565. Fax +44(0)1455 552612.
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Generated
31-Jul-02
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